Geração automática de especificações executáveis em systemc a partir de modelos SysML

Abstract

Embedded system modeling is an important area of research nowadays, and system design become critical as implementation technology progress toward complex integrated circuits and the time-to-market pressure continues to grow. Due to those problems we recognize the necessity to develop methodologies to reduce cost and time spent during all the design phases and system development. SysML, System Modeling Language, is a dedicated system level UML-based notation proposed by OMG. The notation is gaining a lot of importance as a system level design standard because it is a platform independent language, which makes possible the design of systems without knowing implementation details. In this work we propose a tool to support a methodology for automatic translation of some SysML Diagrams (Block Denition Diagram, Internal Block Diagram, State Machine Diagram and Sequence Diagram) to an executable specication in SystemC and demonstrate the usage through a few examples. The proposed approach have some advantages, such as: smaller cost due to project changes, easier documentation and better understanding of the project by stakeholders. The created tool, SysMLToSystemC, was validated by its usage in three systems of dierent natures: two data-oriented systems and one control-driven system. In all three cases, the behavior of the executable specication, automatically generated by the developed tool, was similar to the behavior of the original system or as expected - which is the case of one of the systems with no original source code for comparison.