Projeto e implementação de circuitos classificadores digitais com controle da generalização baseado na regra do vizinho-mais-próximo modificada

Abstract

This work aims at the implementation of classifying binary patterns with digital circuits in order to get a embedded system with the following features: portability, on-line training, operating in real time and with capacity of generalization. The proposed method makes use of training data filtering (or selection) before digital circuit synthesis. It is proposed an algorithm for minimum selection of samples that is based on the k Nearest Neighbor Rule (kNN). This results on a reduced complexity design phase, less resources of storage and processing, and yields also a degree of generalization capacity of the resulting circuit. Some examples of designs of digital classifier circuits generated from synthetic data and real data are presented. The results are compared with others techniques such as Artificial Neural Networks and Support Vector Machines, showing the effectiveness of the proposed method. With the proposed design method, the generated circuit classifier works with less logic gates and with higher generalization capacity than some of the other methods. An implementation in hardware of the method of generation of the proposed circuit classifier is also presented. A solution based on the reconfigurable hardware in FPGA Field Programmable Gate Array with multiprocessing based on the NIOS II processor was adopted. Some measures of performance of the system implemented in hardware are presented, showing the viability of the implementation. Finally, this work has the main contributions: has proposed a new method for sample selection based on kNN; has pressented two new metrics of distance between patterns; has presented a scheme for a digital combinational circuit design working as a binary pattern classifier with generalization capacity; and has presented a proposal for the implementation of a digital classifier system in hardware/software.