Evaluating the impact of interconnections in quantum-dot cellular automata
| dc.creator | Frank Sill Torres | |
| dc.creator | Robert Wille | |
| dc.creator | Marcel Walter | |
| dc.creator | Philipp Niemann | |
| dc.creator | Daniel Grobe | |
| dc.creator | Rolf Drechsler | |
| dc.date.accessioned | 2025-04-16T16:13:09Z | |
| dc.date.accessioned | 2025-09-09T01:31:48Z | |
| dc.date.available | 2025-04-16T16:13:09Z | |
| dc.date.issued | 2018 | |
| dc.identifier.doi | 10.1109/DSD.2018.00110 | |
| dc.identifier.uri | https://hdl.handle.net/1843/81663 | |
| dc.language | eng | |
| dc.publisher | Universidade Federal de Minas Gerais | |
| dc.relation.ispartof | 21st Euromicro Conference on Digital System Design (DSD) | |
| dc.rights | Acesso Restrito | |
| dc.subject | Computação | |
| dc.subject | Nanotecnologia | |
| dc.subject.other | Clocks , Logic gates , Integrated circuit interconnections , Delays , Energy dissipation , Quantum dots , Integrated circuit modeling | |
| dc.subject.other | Quantum dot Cellular Automata, Interconnections, Layout design, Field-Coupled Nanocomputing | |
| dc.subject.other | Quantum-dot Cellular Automata , Energy Cost , Quantification Of The Impact , Design Flow , Delay Cost , Synthesis Method , Increase In Area , Cell Polarity , Synthesis Activity , Synthesis Strategy , Cost Model , Representation Of Function , Sum Of Products , Commercial Tools , Fast Mode , Synthesis Model , Boolean Function , Conventional Circuit , Explicit Element , Cost Metrics , External Clock , Logic Elements | |
| dc.title | Evaluating the impact of interconnections in quantum-dot cellular automata | |
| dc.type | Artigo de evento | |
| local.citation.spage | 649 | |
| local.description.resumo | Quantum-Dot Cellular Automata (QCA) are an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA is based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges rises from the fact that QCA is a planar technology. That means, logic gates as well as interconnection elements are mostly located in the same layer. Hence, it is expected that interconnections have higher influence on the final design costs than in conventional integrated technologies. For the first time, this paper presents an extensive study on the quantification of this impact. Therefore, we consider the entire design flow for QCA circuits from the initial synthesis (using different synthesis approaches) to the corresponding placement on a QCA grid. Then, we characterize the respectively obtained QCA circuits in terms of area, delay and energy costs. The obtained results indicate that the impact of interconnections in QCA is indeed substantial. Design costs including or not including interconnections differ by several orders of magnitudes, which motivates to completely re-think how logic synthesis for QCA circuits shall be conducted in the future. | |
| local.publisher.country | Brasil | |
| local.publisher.department | ENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA | |
| local.publisher.initials | UFMG | |
| local.url.externa | https://ieeexplore.ieee.org/document/8491881 |
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