Processador de asserções para depuração de circuitos integrados em tempo de execução

Abstract

White-box verification is a technique that reduces observabihty problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially,today's verification techniques, such as white-box, can not always ensure a bug free design. This work proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending white-box verification techniques to deployed products helps locate errors that were not found during simulation/emulation phases. We present results of the insertion of assertion checkers and an assertion processor in three different microprocessor cores. We also show that the insertion of these assertion checkers added minimal area and speed overheads to the design.