Ignore clocking constraints: an alternative physical design methodology for field-coupled nanotechnologies

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dc.creatorRobert Wille
dc.creatorMarcel Walter
dc.creatorFrank Sill Torres
dc.creatorDaniel Grobe
dc.creatorRolf Drechsler
dc.date.accessioned2025-05-05T16:06:12Z
dc.date.accessioned2025-09-09T01:23:10Z
dc.date.available2025-05-05T16:06:12Z
dc.date.issued2019
dc.identifier.doi10.1109/ISVLSI.2019.00121
dc.identifier.urihttps://hdl.handle.net/1843/82021
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofIEEE Computer Society Annual Symposium on VLSI (ISVLSI)
dc.rightsAcesso Restrito
dc.subjectNanotecnologia
dc.subject.otherClocks , Logic gates , Magnetization , Physical design , Design methodology , Routing , Wires
dc.subject.otherField Coupled Nanocomputing , Physical Design , Clocking Constraints
dc.subject.otherDesign Methodology , Physical Design , Synchronization , Routing Problem , Physical Simulation , Direct Design , Routing Algorithm , Electronic Design Automation , Stable State , Proof Of Concept , Local Field , Flow Data , Boolean Logic , Circuit Design , Phase Switching , Feedback Path , Routing Method , Small Circuit , Binary Ones , External Clock
dc.titleIgnore clocking constraints: an alternative physical design methodology for field-coupled nanotechnologies
dc.typeArtigo de evento
local.citation.spage651
local.description.resumoField-Coupled Nanocomputing (FCN) allows for conducting computations with a power consumption that is magnitudes below current CMOS technologies. Recent physical implementations confirmed these prospects and put pressure on the Electronic Design Automation (EDA) community to develop physical design methods comparable to those available for conventional circuits. While the major design task boils down to a place and route problem, certain characteristics of FCN circuits introduce further challenges in terms of dedicated clock arrangements which lead to rather cumbersome clocking constraints. Thus far, those constraints have been addressed in a rather unsatisfactory fashion only. In this work, we propose a physical design methodology which tackles this problem by simply ignoring the clocking constraints and using adjusted conventional place and route algorithms. In order to deal with the resulting ramifications, a dedicated synchronization element is introduced. Results extracted from a physics simulator confirm the feasibility of the approach. A proof of concept implementation illustrates that ignoring clocking constraints indeed allows for a promising alternative direction for FCN design that overcomes the obstacles preventing the development of efficient solutions thus far.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/8839546

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