Enhancing fundamental energy limits of field-coupled nanocomputing circuits
| dc.creator | Jeferson F. Chaves | |
| dc.creator | Marco A. Ribeiro | |
| dc.creator | Frank Sill Torres | |
| dc.creator | Omar P. Vilela Neto | |
| dc.date.accessioned | 2025-04-10T14:14:39Z | |
| dc.date.accessioned | 2025-09-08T22:56:57Z | |
| dc.date.available | 2025-04-10T14:14:39Z | |
| dc.date.issued | 2018 | |
| dc.identifier.doi | 10.1109/ISCAS.2018.8351150 | |
| dc.identifier.uri | https://hdl.handle.net/1843/81444 | |
| dc.language | eng | |
| dc.publisher | Universidade Federal de Minas Gerais | |
| dc.relation.ispartof | International Symposium on Circuits and Systems (ISCAS) | |
| dc.rights | Acesso Restrito | |
| dc.subject | Semicondutores complementares de oxido metalico | |
| dc.subject | Circuitos integrados lineares | |
| dc.subject.other | Logic gates , Recycling , Delays , Benchmark testing , Energy dissipation , Quantum dots , Computer architecture | |
| dc.subject.other | Fundamental Limitation , Fundamental Energy , Benchmark , Recycling , Dissipation , Time And Space , Space Complexity , Boolean Logic , Complex Circuits , Exponential Time , Input Bits , Degradation Cost , Complementary Metal Oxide Semiconductor Technology | |
| dc.subject.other | the future advancement of Complementary Metal-Oxide Semiconductor (CMOS) technology systems could be strongly restricted by energy dissipation issues | |
| dc.title | Enhancing fundamental energy limits of field-coupled nanocomputing circuits | |
| dc.type | Artigo de evento | |
| local.citation.epage | 5 | |
| local.citation.spage | 1 | |
| local.description.resumo | Energy dissipation of future integrated systems, consisting of a myriad of devices, is a challenge that cannot be solved solely by emerging technologies and process improvements. Even though approaches like Field-Coupled Nanocomputing allow computations near the fundamental energy limits, there is a demand for strategies that enable the recycling of bits' energy to avoid thermalization of information. In this direction, we propose a new kind of partially reversible systems by exploiting fan-outs in logic networks. We have also introduced a computationally efficient method to evaluate the gain obtained by our strategy. Simulation results for state-of-the-art benchmarks indicate an average reduction of the fundamental energy limit by 17% without affecting the delay. If delay is not the main concern, the average reduction reaches even 51%. To the best of our knowledge, this work presents the first post-synthesis strategy to reduce fundamental energy limits for Field-Coupled Nanocomputing circuits. | |
| local.publisher.country | Brasil | |
| local.publisher.department | ENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA | |
| local.publisher.department | ICX - DEPARTAMENTO DE CIÊNCIA DA COMPUTAÇÃO | |
| local.publisher.initials | UFMG | |
| local.url.externa | https://ieeexplore.ieee.org/document/8351150 |
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