Hardware/Software implementation factors influencing ethernet latency

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dc.creatorTomás Perpetuo Corrêa
dc.creatorLuís Miguel Pinho de Almeida
dc.creatorEmilio Jose Bueno Peña
dc.date.accessioned2025-04-09T14:41:58Z
dc.date.accessioned2025-09-09T00:19:28Z
dc.date.available2025-04-09T14:41:58Z
dc.date.issued2018
dc.identifier.doi10.1109/INDIN.2018.8472002
dc.identifier.urihttps://hdl.handle.net/1843/81406
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartof16th International Conference on Industrial Informatics (INDIN)
dc.rightsAcesso Restrito
dc.subjectEthernet (Sistema de rede local de computação)
dc.subjectSistemas operacionais (Computadores)
dc.subject.otherDelays , IP networks , Protocols , Software , Hardware , Clocks , Real-time systems
dc.subject.otherIndustrial communication systems , real-time Ethernet , end-to-end latency
dc.subject.otherPerformance Indicators , Application Layer , Hardware Accelerators , Data Rate , Transfer Rate , Data Transfer , Physical Layer , Packet Size , Protocol Stack , Device Memory , Host PC , Packet Processing
dc.subject.otherIndustrial Internet of Things and Industry 4.0
dc.subject.otherEthernet é uma tecnologia de rede que permite a conexão física entre computadores, impressoras e roteadores em redes locais (LAN)
dc.titleHardware/Software implementation factors influencing ethernet latency
dc.typeArtigo de evento
local.description.resumoMinimum Cycle Time is a common performance indicator adopted to compare Real-Time Ethernet protocols. Though serving its purpose, Minimum Cycle Time excludes the delays inside the sending and receiving nodes, so it is insufficient to estimate the end-to-end latency. In this work, we describe some implementation possibilities of an Ethernet node in a System-on-Chip and present measurements of the delay to send/receive packets from/to the application layer. We chose different points in the software to make the measurement, so the results cover more use-cases. We found the Ethernet Lite Media Access Controller (MAC) to be faster than the hard MAC (GEM) and the Lightweight IP stack to add less than 2.2 μs. Finally, we show how a hardware accelerator can reduce the delay of high-priority packets by 1.4 μs.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/8472002

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