HotAging: impact of power dissipation on hardware degradation
| dc.creator | Frank Sill Torres | |
| dc.creator | Alberto Garcia Ortiz | |
| dc.creator | Rolf Drechsler | |
| dc.date.accessioned | 2025-05-07T14:08:24Z | |
| dc.date.accessioned | 2025-09-08T23:10:43Z | |
| dc.date.available | 2025-05-07T14:08:24Z | |
| dc.date.issued | 2019 | |
| dc.identifier.doi | 10.1109/ISCAS.2019.8702073 | |
| dc.identifier.uri | https://hdl.handle.net/1843/82081 | |
| dc.language | eng | |
| dc.publisher | Universidade Federal de Minas Gerais | |
| dc.relation.ispartof | International Symposium on Circuits and Systems (ISCAS) | |
| dc.rights | Acesso Restrito | |
| dc.subject | Circuitos integrados | |
| dc.subject.other | Reliability, Aging , Delays , Degradation , Libraries , Power dissipation , Temperature , Integrated circuit modeling | |
| dc.subject.other | Aging , Temperature , BTI , Degradation , Power | |
| dc.subject.other | Worst Case , Input Vector , Dependability , Maximum Delay , High Dissipation , Considerable Temperature , Random Vector , Impact Of Temperature , Reference Temperature , Active Switches , Acceleration Factor , Hot Electrons , Parental Genomes , Cell Library , Critical Path , Random Input , Power Profile , Path Delay | |
| dc.title | HotAging: impact of power dissipation on hardware degradation | |
| dc.type | Artigo de evento | |
| local.citation.spage | 1 | |
| local.description.resumo | Safety and dependability are of utmost importance for many integrated systems. Hence, it must be guaranteed throughout the whole system's lifetime that no ambient and internal influences can affect the system's integrity. Under this scope and having in mind the side-effects of today's nanoscale technologies, hardware degradation is of rising concern. However, related studies should not solely focus on aging effect itself, but also consider its relation to any accelerating factors, especially temperature. Towards this end, this work presents a study on how the power dissipation of a circuit, and thus, its temperature, can expedite wear-out effects. Therefore, three different analysis are performed-aging without and with consideration of temperature and the study on how guard-banding strategies are affected. In order to distinguish random and, maliciously intended or accidentally produced, worst case scenarios, we implemented an algorithm that determines a combination of input vectors that forces high aging states and high power dissipation. Results indicate that aging under consideration of temperature can increase circuit delay by more than 26% (random case) and by nearly 40% (worst case). That means, if a maximum acceptable delay degradation is defined, designs can enter malfunction states already in a period of weeks (worst case) or months (random case). These results underline the importance of considering power dissipation, and thus temperature, when doing aging analysis and aging verification. | |
| local.publisher.country | Brasil | |
| local.publisher.department | ENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA | |
| local.publisher.initials | UFMG | |
| local.url.externa | https://ieeexplore.ieee.org/document/8702073 |
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