Projeto de um Phase-Locked Loop de baixo Jitter em tecnologia CMOS

Abstract

With the constant technological evolution, the demand for higher processing speeds in digital systems is also continuous. Clock multiplier are circuits responsible for generating a higher frequency signal from a reference signal of lower frequency, like a piezoelectric crystal, for example. The Phase-Locked Loop (PLL) is the basis of this circuit and is the focus of different studies, in the search for better experimental results that, consequently, will have a positive impact on quality spectral output signal of the clock multiplier circuit. This work presents the design of a Type I PLL in 180 nm CMOS technology, based on a VCO in ring topology, with a divider in the feedback loop, a phase detector in a dynamic topology, in addition to a new filter proposal, based on equivalent resistance generated as a function of switched capacitors. Descriptions and simulations of each circuit block are presented, discussed and validated so that the final circuit is presented, as well as your simulation and layout. With a division factor of 32 and a reference signal of 50 MHz, the simulations of proposed topology presented a bandwidth of 25 MHz, a phase noise of -118 dBc/Hz at 1 MHz offset, 486 fs of built-in jitter and REF-spur levels of -63 dB. Also, although the technology used is not the latest, this circuit has a low power consumption, 10 mW, in addition to a total area of 0.0105 mm². These results were compared with other works showing that this proposal is compatible with the state of the art on PLL.