Minimal digital chaotic system

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dc.creatorErivelton Geraldo Nepomuceno
dc.creatorArthur Mendes Lima
dc.creatorJanier Arias García
dc.creatorMatjaz Perc
dc.creatorRobert Repnik
dc.date.accessioned2025-05-21T14:13:31Z
dc.date.accessioned2025-09-09T01:32:15Z
dc.date.available2025-05-21T14:13:31Z
dc.date.issued2019
dc.identifier.doihttps://doi.org/10.1016/j.chaos.2019.01.019
dc.identifier.issn0960-0779
dc.identifier.urihttps://hdl.handle.net/1843/82414
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofChaos, solitons and fractals
dc.rightsAcesso Restrito
dc.subjectSistemas dinâmicos
dc.subject.otherNonlinear dynamics
dc.subject.otherFPGA synthesis
dc.subject.otherComputer arithmetic,
dc.subject.otherDigital system
dc.titleMinimal digital chaotic system
dc.typeArtigo de periódico
local.citation.epage66
local.citation.spage62
local.citation.volume120
local.description.resumoOver the past few decades, many works have been devoted to designing simple chaotic systems based on analog electronic circuits. However, the same attention is not observed in digital chaotic systems. This paper presents a design of a digital chaotic system using a digit complement. This special case of fixed-point number representation allows us to reduce the silicon area and the number of logic elements to perform the arithmetic operations. The design presents a configurable number of bits, and it is based on the logistic map. The proposed circuit has been implemented on a reconfigurable hardware, FPGA Cyclone V, showing that the number of logic elements has been significantly reduced compared to other works in the literature.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://www.sciencedirect.com/science/article/pii/S0960077919300219

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