Improving the efficiency of gabriel graph-based classifiers for hardware-optimized implementations

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dc.creatorAlan C. Souza
dc.creatorCristiano Leite de Castro
dc.creatorJanier Arias García
dc.creatorLuiz Carlos Bambirra Torres
dc.creatorLeidy J. Acevedo Jaimes
dc.creatorBrayan R. A. Jaimes
dc.date.accessioned2025-05-05T16:30:44Z
dc.date.accessioned2025-09-08T23:50:00Z
dc.date.available2025-05-05T16:30:44Z
dc.date.issued2019
dc.identifier.doi10.1109/STSIVA.2019.8730227
dc.identifier.urihttps://hdl.handle.net/1843/82027
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofXXII Symposium on Image, Signal Processing and Artificial Vision (STSIVA)
dc.rightsAcesso Restrito
dc.subjectComputadores (Engenharia)
dc.subject.otherHardware , Field programmable gate arrays , Computational modeling , Numerical models , Data models , Analytical models , Parallel processing
dc.subject.otherClassification , Gabriel graph , FPGA , numerical representation , parallel computing
dc.subject.otherRunning Time , Analysis Of The Impact , Precise Model , Low Precision , Hardware Implementation , Least Significant Bit , Parallel Algorithm , Double Precision , Parallel Technique , Machine Learning , Model Performance , Training Data , Exponential Growth , Average Results , Graphics Processing Unit , Class Labels , Resource Consumption , Hyperplane , Reference Model , Graph Structure , Hardware Architecture , Vertex Degree , Single Precision , Numerical Representation , Filtering Techniques
dc.titleImproving the efficiency of gabriel graph-based classifiers for hardware-optimized implementations
dc.typeArtigo de evento
local.description.resumoThis work evaluates strategies to reduce the computational cost of Gabriel graph-based classifiers, in order to make them more suitable for hardware implementation. An analysis of the impact of the bit precision provides insights on the model's robustness for lower precision arithmetic. Additionally, a parallelization technique is proposed in order to improve the efficiency of the support edges computation. The results show that the lower bit precision models are statistically equivalent to the reference double-precision ones. Also, the implementation of the proposed parallel algorithm provides a significant reduction in the running time when applied in large datasets, while maintaining its accuracy.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELÉTRICA
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/8730227

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