Verificação formal na indústria

Abstract

Formal Methods is a group of system design techniques that use mathematics formalism to assist specification, development and verification steps. The approach can reduce specifications ambiguities and inconsistences, provide automatic automated code generation and automate verifying tasks, showing up as an alternative to achieve systems with higher correctness levels, especially in cases that failures can lead to major material and human losses. This study consists of an evaluation of formal methods in industry with a real case presentation of a formal verification software used in integrated circuits industry. Seeing that, are shown the concepts related to the field, the main specification and verification formal methods, the challenges faced by the methodology for establishing in the market and suggestions to overcome them. Finally, it is shown the Cadence Design Systemss formal verification software JasperGold Apps, its structure and implemented techniques, as well as the formal approach significance and benefits in hardware industry.