A new Cross-by-Pass-Torus architecture based on CBP-mesh and torus interconnection for on-chip communication

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dc.creatorUsman Ali Gulzari
dc.creatorMuhammad Sajid
dc.creatorSheraz Anjum
dc.creatorShahrukh Agha
dc.creatorFrank Sill Torres
dc.date.accessioned2025-03-26T14:20:44Z
dc.date.accessioned2025-09-09T00:57:06Z
dc.date.available2025-03-26T14:20:44Z
dc.date.issued2016
dc.identifier.doi10.1371/journal.pone.0167590
dc.identifier.issn1932-6203
dc.identifier.urihttps://hdl.handle.net/1843/80938
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofPLoS ONE
dc.rightsAcesso Restrito
dc.subjectSistema em um chip
dc.subjectRedes de computadores
dc.subjectSistemas embutidos de computador
dc.subject.otherNetwork on Chip (NOC)
dc.subject.otherplacement of extra links in 2D Mesh architecture for interconnecting the nodes of the network can play an important role in achieving high performance with low cost
dc.subject.otherCBP-Torus architecture design
dc.titleA new Cross-by-Pass-Torus architecture based on CBP-mesh and torus interconnection for on-chip communication
dc.typeArtigo de periódico
local.citation.issue12
local.citation.spagee0167590
local.citation.volume11
local.description.resumoA Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor’s and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://journals.plos.org/plosone/article?id=10.1371/journal.pone.0167590

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