Design and verification of a parameterizable interleaver and deinterleaver for visible light communication

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dc.creatorMateus Gonçalves Silva
dc.creatorGabriel R. T. Araújo
dc.creatorElisa S. Bacelar
dc.creatorRicardo de Oliveira Duarte
dc.date.accessioned2025-05-23T12:43:46Z
dc.date.accessioned2025-09-09T01:03:19Z
dc.date.available2025-05-23T12:43:46Z
dc.date.issued2020
dc.identifier.urihttps://hdl.handle.net/1843/82466
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartof10ᵗʰ Workshop on Circuits and Systems Design
dc.rightsAcesso Aberto
dc.subjectComunicações óticas
dc.subject.otherInterleaver
dc.subject.otherVLC
dc.subject.otherPHY, Reusable IP
dc.subject.otherThe process of data exchange in any communication channel is sub-jected to interference from the environment that may cause errorsin the transmitted data. These errors can be individual or burstsof bit ips. Burst errors are harmful because they may easilyviolate the maximum capacity of Error Correction Codes (ECC)employed by communication systems. Interleavers are designed inorder to mitigate such disturbance caused by burst errors. They arepresent in many communication standards such as HSPA+, 3GPP,WiMAX, WLAN, and DVB-T/H.
dc.titleDesign and verification of a parameterizable interleaver and deinterleaver for visible light communication
dc.typeArtigo de evento
local.description.resumoThis paper proposes an open IP block of a parameterizable inter-leaver and deinterleaver for Visible Light Communication (VLC). Architectural details, verification methodology, and FPGA synthesis are explored for the implemented digital design. Achieved results in device utilization and performance are comparable to available commercial IPs and met throughput requirements of the target application.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://www.researchgate.net/publication/349726885

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