Conversor digital para o tempo do tipo Vernier implementado em FPGA

Abstract

This work presents a Digital-to-Time Converter (DTC) based on a low-cost FPGA platform, employing the Vernier with oscillators architecture. A DTC is a circuit that converts digital information into a very accurate time output. This work is implemented on an Altera Cyclone III FPGA chip and features tunable resolution through the period ratio between two PLL-generated signals. The linearity of the system was measured for a resolution of 990 ps, showing DNL and INL values of -0.41 to +0.54 LSB and -0.82 to +0.17 LSB, respectively. The proposed Vernier DTC has a range of 99 ns and an estimated power consumption of 89 mW. Furthermore, measurements demonstrate that the system achieves a maximum resolution of 12.5 ps, utilizing only 2% of the FPGA resources. Additionally, the logical and physical synthesis of the proposed design was carried out using a commercial 350 nm CMOS technology, and the estimated power consumption and silicon area are 1.75 mW, and 237 µm x 190 µm, respectively.