DSCC-MMC STATCOM main circuit parameters design considering positive and negative sequence compensation

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dc.creatorAllan Fagner Cupertino
dc.creatorJoão Victor Matos Farias
dc.creatorHeverton Augusto Pereira
dc.creatorSeleme Isaac Seleme Junior
dc.creatorRemus Teodorescu
dc.date.accessioned2025-04-03T16:20:39Z
dc.date.accessioned2025-09-08T23:53:31Z
dc.date.available2025-04-03T16:20:39Z
dc.date.issued2017
dc.identifier.doi10.1007/s40313-017-0349-4
dc.identifier.issn2195-3880
dc.identifier.urihttps://hdl.handle.net/1843/81275
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofJournal of control, automation and electrical systems
dc.rightsAcesso Restrito
dc.subjectConversores eletrônicos
dc.subjectCircuitos integrados lineares
dc.subject.otherpower quality issues arise in the modern medium voltage (MV) distribution systems due to the high penetration of nonlinear and unbalanced loads
dc.subject.otherloads can lead to current distortions, uncontrollable reactive power, unbalances and voltage flicker
dc.titleDSCC-MMC STATCOM main circuit parameters design considering positive and negative sequence compensation
dc.typeArtigo de periódico
local.citation.epage74
local.citation.spage62
local.citation.volume29
local.description.resumoThe double-star chopper cell modular multilevel converter (DSCC-MMC) has been employed in several applications as HVDC, energy storage, renewable energy, electrical drives and STATCOMs. Generally, the DSCC-MMC main circuit parameter design presented in literature considers balanced currents flowing through the converter. Nevertheless, in STATCOM application, the converter can compensate negative sequence components and unbalanced currents flow through the DSCC-MMC, resulting in different stresses in the converter phases. Therefore, this work presents a detailed design methodology of the DSCC-MMC main circuit parameters, considering both positive and negative sequence current compensations. The dc-link voltage, number of submodules, power semiconductor thermal stresses, submodule capacitance and arm inductances are designed. Expressions for the energy storage requirements are derived when negative sequence is compensated. A case study considering a 15-MVA STATCOM is presented, and simulation results validate the proposed design methodology. Finally, the converter power losses and thermal stresses in the power semiconductors are evaluated.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELÉTRICA
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://link.springer.com/article/10.1007/s40313-017-0349-4

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