Automatic fault injection into SystemC designs

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dc.creatorTúlio Paschoalin Leão
dc.creatorFrank Sill Torres
dc.date.accessioned2025-03-25T16:01:06Z
dc.date.accessioned2025-09-09T00:58:57Z
dc.date.available2025-03-25T16:01:06Z
dc.date.issued2016
dc.identifier.urihttps://hdl.handle.net/1843/80908
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartof6th Workshop on Circuits and System Design
dc.rightsAcesso Aberto
dc.subjectComputação
dc.subjectSoftware - Desenvolvimento
dc.subject.otherSystemC
dc.subject.otherReliability of component, Reliability of design
dc.subject.otherprogramming languages
dc.subject.othercomponent’s variable
dc.subject.otherTLM, fault injection, fault coverage
dc.titleAutomatic fault injection into SystemC designs
dc.typeArtigo de evento
local.description.resumoThis paper introduces a flow for automatic fault injection into plain SystemC and SystemC/TLM (Transaction Level Modeling) designs. The aim of this flow is reducing the complexity of reliability analysis and fault coverage determination of complex designs. The flow enables the consideration of transitory and permanent faults, which can be applied in directed or random manner. Thereby, faults are represented as faulty values of variables, which are automatically identified during an initial phase. The implemented flow was successfully applied for all example designs provided by the official SystemC library. Further, the utilization of the algorithm for an exemplary technique for robustness enhancement, namely the Triple Modular Redundancy, could prove the viability of proposed flow.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://franksilltorres.de/downloads/paper/Leao-WCAS2016.pdf

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