A hardware-efficient perturbation method to the digital tent map
| dc.creator | Lucas Nardo | |
| dc.creator | Erivelton Nepomuceno | |
| dc.creator | Daniel Muñoz | |
| dc.creator | Denis Butusov | |
| dc.creator | Janier Arias García | |
| dc.date.accessioned | 2025-05-27T14:33:56Z | |
| dc.date.accessioned | 2025-09-09T00:11:33Z | |
| dc.date.available | 2025-05-27T14:33:56Z | |
| dc.date.issued | 2023 | |
| dc.identifier.doi | 10.3390/electronics12081953 | |
| dc.identifier.issn | 20799292 | |
| dc.identifier.uri | https://hdl.handle.net/1843/82523 | |
| dc.language | eng | |
| dc.publisher | Universidade Federal de Minas Gerais | |
| dc.relation.ispartof | Electronics | |
| dc.rights | Acesso Aberto | |
| dc.subject | Sistemas dinâmicos | |
| dc.subject.other | chaotic map; computer arithmetic; digital system; hardware architecture; pseudo-random number generator; particle swarm optimization | |
| dc.title | A hardware-efficient perturbation method to the digital tent map | |
| dc.type | Artigo de periódico | |
| local.citation.issue | 8 | |
| local.citation.spage | 1953 | |
| local.citation.volume | 12 | |
| local.description.resumo | Digital chaotic systems used in various applications such as signal processing, artificial intelligence, and communications often suffer from the issue of dynamical degradation. This paper proposes a solution to address this problem in the digital tent map. Our proposed method includes a simple and optimized hardware architecture, along with a hardware-efficient perturbation method, to create a high-performance computing system that retains its chaotic properties. We implemented our proposed architecture using an FPGA (Field-Programmable Gate Array) and the 1’s complement fixed-point format. Our results demonstrate that the implemented digital circuit reduces logical resource consumption compared to state-of-the-art references and exhibits pseudo-random nature, as confirmed by various statistical tests. We validated our proposed pseudo-random number generator in a hardware architecture for particle swarm optimization, demonstrating its effectiveness. | |
| local.publisher.country | Brasil | |
| local.publisher.department | ENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA | |
| local.publisher.initials | UFMG | |
| local.url.externa | https://www.mdpi.com/2079-9292/12/8/1953 |