Mitigation of aging effects through selective time-borrowing and alternative path activation
| dc.creator | Andrei dos Santos Silva | |
| dc.creator | Frank Sill Torres | |
| dc.date.accessioned | 2025-03-28T16:57:55Z | |
| dc.date.accessioned | 2025-09-08T23:46:34Z | |
| dc.date.available | 2025-03-28T16:57:55Z | |
| dc.date.issued | 2017 | |
| dc.identifier.uri | https://hdl.handle.net/1843/81079 | |
| dc.language | eng | |
| dc.publisher | Universidade Federal de Minas Gerais | |
| dc.relation.ispartof | 30th Symposium on Integrated Circuits and Systems Design (SBCCI) | |
| dc.rights | Acesso Restrito | |
| dc.subject | Aprendizado do computador | |
| dc.subject | Topologia algébrica | |
| dc.subject.other | Delays , Aging , Clocks , Flip-flops , Fans , Topology | |
| dc.subject.other | Aging , Timing faults , Time-borrowing , Processor | |
| dc.subject.other | Alternative Activation , Correct Value , Error Detection , Critical Path , Digital Circuits , Test Circuit , Power Overhead , Learning Algorithms , Multiplexing , Inverter , Error Signal , Compressor , Supply Voltage , Sequential Stages , Clock Frequency , Clock Cycles , Design Flow , Path Selection , Path Delay , Area Overhead | |
| dc.title | Mitigation of aging effects through selective time-borrowing and alternative path activation | |
| dc.type | Artigo de evento | |
| local.citation.spage | 210 | |
| local.description.resumo | Integrated digital circuits are frequency capped by its heavily constrained paths between flip-flop stages. These so-called critical paths are highly susceptible to delay fluctuations leading designers to use guard-banding in order to avoid timing violations. Several effects can cause these variations, whereas aging is of rising importance. Many works have addressed this issue through monitoring of critical paths or techniques for error detection. The consequent error correction, however, requires the interruption of the circuit's operation for restoration of correct values, resulting into a performance drop. This work proposes two strategies tackling this problem without cycle loss: A time-borrowing approach that redistributes the slack between a critical path and its most constrained fan out paths; and the technique Alternative Path Activation (APA) which applies duplication of the most time-constrained fan out paths of a critical path. Simulations were conducted for several test circuits indicating its feasibility. Further, the proposed approach was implemented in ARMv2 based processor core, resulting in an enhanced robustness against aging induced delay variations of 7.2 % at the cost of 2.5 % area and 2.7 % power overhead. | |
| local.publisher.country | Brasil | |
| local.publisher.department | ENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA | |
| local.publisher.initials | UFMG | |
| local.url.externa | https://ieeexplore.ieee.org/document/8088581 |
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