Cell library design for ultra-low power Internet-of-Things applications
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Universidade Federal de Minas Gerais
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A wide range of applications in the field of the Internet-of-Things (IoT) possess only strongly limited energy resources. This rises the need for Ultra-Low Power (ULP) designs that enable processing with lowest energy consumption. This, however, comes at considerable performance costs. Consequently, there is a need for flexible design flows that enable the designer to select the best tradeoff between energy consumption and performance for the destined application. Towards this end, we present in this paper a complete flow for the design of a ULP standard cell library based on the subthreshold methodology. The flow considers both the selection of the appropriate technology parameters, like supply voltage and base sizing, as well as the actual design and characterization of the standard cells. Simulation results for an ARM-based processor and ITC'99 and EPFL benchmark circuits realized in a commercial 130 nm technology indicate a possible reduction of power consumption of several factors, while performance degrades between two and three orders of magnitude.
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Internet das coisas, Eletrônica de potência
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Standards , Libraries , Delays , Energy consumption , Transistors , Logic gates , Threshold voltage, Ultra-low power , Internet-of-Things , Energy consumption , Standard cell library , Subthreshold Design, Cell Library , Library Design , Ultra-low Power , Benchmark , Energy Consumption , Characteristics Of Cells , Supply Voltage , Standard Library , Appropriate Technology , Design Flow , Lowest Energy Consumption , Parasite , Carrier Mobility , First Approximation , Multi-objective Optimization , Threshold Voltage , Radio Frequency Identification , Test Bench , Minimum Width , Output Load , Transistor Size , Gate Length , Electronic Design Automation , Technology Node , Strong Inversion , Gate Oxide , Test Circuit , Circuit Size , Total Dissipation
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https://ieeexplore.ieee.org/document/8546716