Cell library design for ultra-low power Internet-of-Things applications

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dc.creatorMichael Lopes de Oliveira
dc.creatorFrank Sill Torres
dc.creatorKeyliane da Silva Fernandes
dc.date.accessioned2025-04-14T17:39:00Z
dc.date.accessioned2025-09-08T23:31:28Z
dc.date.available2025-04-14T17:39:00Z
dc.date.issued2018
dc.identifier.doi10.1109/INSCIT.2018.8546716
dc.identifier.urihttps://hdl.handle.net/1843/81558
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartof3rd International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT)
dc.rightsAcesso Restrito
dc.subjectInternet das coisas
dc.subjectEletrônica de potência
dc.subject.otherStandards , Libraries , Delays , Energy consumption , Transistors , Logic gates , Threshold voltage
dc.subject.otherUltra-low power , Internet-of-Things , Energy consumption , Standard cell library , Subthreshold Design
dc.subject.otherCell Library , Library Design , Ultra-low Power , Benchmark , Energy Consumption , Characteristics Of Cells , Supply Voltage , Standard Library , Appropriate Technology , Design Flow , Lowest Energy Consumption , Parasite , Carrier Mobility , First Approximation , Multi-objective Optimization , Threshold Voltage , Radio Frequency Identification , Test Bench , Minimum Width , Output Load , Transistor Size , Gate Length , Electronic Design Automation , Technology Node , Strong Inversion , Gate Oxide , Test Circuit , Circuit Size , Total Dissipation
dc.titleCell library design for ultra-low power Internet-of-Things applications
dc.typeArtigo de evento
local.citation.spage1
local.description.resumoA wide range of applications in the field of the Internet-of-Things (IoT) possess only strongly limited energy resources. This rises the need for Ultra-Low Power (ULP) designs that enable processing with lowest energy consumption. This, however, comes at considerable performance costs. Consequently, there is a need for flexible design flows that enable the designer to select the best tradeoff between energy consumption and performance for the destined application. Towards this end, we present in this paper a complete flow for the design of a ULP standard cell library based on the subthreshold methodology. The flow considers both the selection of the appropriate technology parameters, like supply voltage and base sizing, as well as the actual design and characterization of the standard cells. Simulation results for an ARM-based processor and ITC'99 and EPFL benchmark circuits realized in a commercial 130 nm technology indicate a possible reduction of power consumption of several factors, while performance degrades between two and three orders of magnitude.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/8546716

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