Pipelined SAR with comparator-based switch-capacitor residue amplification
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Universidade Federal de Minas Gerais
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This work presents the implementation of an 11 Bit pipelined successive approximation register ADC (PSAR) in a 65 nm technology. The proposed ADC utilizes comparator-based switch-capacitor circuits and zero-detection in order to enable fast and high linear residue amplification with at reasonable area costs. Simulation results indicate conversion rates of 4.4 MSPS and energy consumption of 48.8 fJ per step.
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Circuitos integrados digitais
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Analog-digital conversion, Capacitors, Switches, Inverters, Switching circuits, Registers, Simulation, Switched capacitor circuits, Analog-digital integrated circuits, Zero-Crossing Detection