Pipelined SAR with comparator-based switch-capacitor residue amplification

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dc.creatorFrank Sill Torres
dc.creatorPedro Henrique Kohler Marra Pinto
dc.date.accessioned2024-10-09T16:09:31Z
dc.date.accessioned2025-09-08T23:11:07Z
dc.date.available2024-10-09T16:09:31Z
dc.date.issued2016-02
dc.identifier.doi10.1109/LASCAS.2016.7451024
dc.identifier.issn2473-4667
dc.identifier.urihttps://hdl.handle.net/1843/77332
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.rightsAcesso Restrito
dc.subjectCircuitos integrados digitais
dc.subject.otherAnalog-digital conversion
dc.subject.otherCapacitors
dc.subject.otherSwitches
dc.subject.otherInverters
dc.subject.otherSwitching circuits
dc.subject.otherRegisters
dc.subject.otherSimulation
dc.subject.otherSwitched capacitor circuits
dc.subject.otherAnalog-digital integrated circuits
dc.subject.otherZero-Crossing Detection
dc.titlePipelined SAR with comparator-based switch-capacitor residue amplification
dc.typeArtigo de evento
local.citation.epage122
local.citation.issue2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)
local.citation.spage119
local.description.resumoThis work presents the implementation of an 11 Bit pipelined successive approximation register ADC (PSAR) in a 65 nm technology. The proposed ADC utilizes comparator-based switch-capacitor circuits and zero-detection in order to enable fast and high linear residue amplification with at reasonable area costs. Simulation results indicate conversion rates of 4.4 MSPS and energy consumption of 48.8 fJ per step.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG

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