Single event upset rate determination for 65nm SRAM bit-cell in LEO radiation environments

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dc.creatorMuhammad Sajid
dc.creatorNikolay Chechenin
dc.creatorFrank Sill Torres
dc.creatorUsman Ali Gulzari
dc.creatorMuhammad Usman Butt
dc.creatorZhu Ming
dc.creatorEhsan Ullah Khan
dc.date.accessioned2025-04-03T15:54:29Z
dc.date.accessioned2025-09-09T00:29:58Z
dc.date.available2025-04-03T15:54:29Z
dc.date.issued2017
dc.identifier.doihttps://doi.org/10.1016/j.microrel.2017.07.084
dc.identifier.issn0026-2714
dc.identifier.urihttps://hdl.handle.net/1843/81271
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofMicroelectronics reliability
dc.rightsAcesso Restrito
dc.subjectSemicondutores complementares de óxido metálico
dc.subjectCircuitos de sinais mistos
dc.subjectCircuitos eletrônicos - Projetos
dc.subject.otherAn SEU rate estimation approach based on a heavy ion cross section as opposed to the standard experimental characterization
dc.subject.otherSEU map shows 65 nm SRAM bit-cell can change state even if high LET particle strikes in close proximity of bit-cell area
dc.subject.otherThe cost-effective MC TCAD simulations to determine the SEU cross-section/SEU rate of highly scaled advanced CMOS devices
dc.subject.otheridentification of vulnerable or weak points of CMOS layout designs for specific radiation environment
dc.subject.otherapplicable to various memory and logic device for estimation of their radiation response
dc.titleSingle event upset rate determination for 65nm SRAM bit-cell in LEO radiation environments
dc.typeArtigo de periódico
local.citation.epage16
local.citation.spage11
local.citation.volume78
local.description.resumohe degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://www.sciencedirect.com/science/article/pii/S0026271417303554

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