Design of an advanced system-on-chip architecture for chaotic image encryption

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dc.creatorArthur M. Lima
dc.creatorLucas G. Nardo
dc.creatorErivelton Nepomuceno
dc.creatorJanier Arias García
dc.creatorJones Yudi
dc.date.accessioned2025-06-02T11:45:05Z
dc.date.accessioned2025-09-08T22:57:11Z
dc.date.available2025-06-02T11:45:05Z
dc.date.issued2023
dc.identifier.doihttps://doi.org/10.1109/SBCCI60457.2023.10261963
dc.identifier.urihttps://hdl.handle.net/1843/82678
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartof36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)
dc.rightsAcesso Restrito
dc.subjectProcessamento de sinais - Técnicas digitais
dc.subject.otherPerformance evaluation , Chaotic communication , System performance , Heuristic algorithms , Reconfigurable logic , Interconnected systems , Encryption
dc.subject.otherSystem-on-Chip , chaos , chaotic systems , image encryption , finite-precision error , latency-sensitive applications
dc.subject.otherImage Encryption , Chaotic System , Cryptosystem , Encryption System , Benchmark Images , Uniform Distribution , Lookup Table , Natural Extension , Digital Signal Processing , Random Access Memory , Encryption Scheme , Stream Channel , Programmable Logic , High-level Synthesis , Bitwise Operations , Pixel Correlation , Differential Attacks
dc.titleDesign of an advanced system-on-chip architecture for chaotic image encryption
dc.typeArtigo de evento
local.citation.spage1
local.description.resumoWith the rise of interconnected systems, security has become a crucial concern. As a result, there has been a growing interest in developing low-cost embedded cryptographic algorithms that are lightweight and can be integrated into System-on-Chip (SoC) devices. Digital chaotic systems have emerged as a promising approach for building secure communication systems, where various cryptosystems utilize chaotic dynamics to encrypt images into noise-like representations. Recent studies have demonstrated that finite-precision error can be used to derive chaos, which can be systematically applied to encrypt images. However, there is a lack of research on how SoC-based design constraints affect the overall performance of image encryption systems, especially for applications that are sensitive to latency. This study aims to address this gap by presenting an efficient architecture that explores a hardware/software co-design for image encryption based on finite-precision error, specifically designed for resource-limited devices and latency-sensitive applications. Our platform performs the capture and encryption of images with a size of 320 × 240. Using a benchmark image, results show that the developed cryptosystem architecture can encrypt images efficiently while offering low hardware occupation.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/10261963

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