Designing partially reversible field-coupled nanocomputing circuits

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dc.creatorJeferson Figueiredo Chaves
dc.creatorMarco Antônio Ribeiro
dc.creatorFrank Sill Torres
dc.creatorOmar Paranaiba Vilela Neto
dc.date.accessioned2025-05-15T13:17:13Z
dc.date.accessioned2025-09-08T23:02:05Z
dc.date.available2025-05-15T13:17:13Z
dc.date.issued2019
dc.identifier.doi10.1109/TNANO.2019.2918057
dc.identifier.issn1536125X
dc.identifier.urihttps://hdl.handle.net/1843/82289
dc.languageeng
dc.publisherUniversidade Federal de Minas Gerais
dc.relation.ispartofIEEE Transactions on Nanotechnology
dc.rightsAcesso Restrito
dc.subjectComputação
dc.subject.otherLogic gates , Entropy , Energy dissipation , Delays , Quantum dots , Energy loss , Scalability
dc.subject.otherReversible computing , nanocomputing , energy efficiency , low power
dc.subject.otherPartial Reversal , Reversible Logic , Benchmark , Energy Efficiency , Fundamental Limitation , Logical Networks , Fundamental Energy , Recycling , Environmental Temperature , Energy Loss , Boltzmann Constant , Reverse Order , Shannon Entropy , Energy Rate , Energy Reduction , Enthalpy Of Formation , Law Of Thermodynamics , Second Law Of Thermodynamics , Primary Input , Complementary Metal Oxide Semiconductor Technology , OR Gate , Input Bits , Input Probability
dc.titleDesigning partially reversible field-coupled nanocomputing circuits
dc.typeArtigo de periódico
local.citation.epage597
local.citation.spage589
local.citation.volume18
local.description.resumoEnergy scalability of future digital systems is bounded by fundamental thermodynamic limits. Even worse, emerging technologies and process improvements, without reversible techniques, cannot solve this problem. Approaches such as field-coupled nanocomputing allow computations near the fundamental energy limits. However, there is a demand for strategies that avoid information losses within logic gates, consequently improving energy efficiency. For that end, we propose a novel way to reduce such losses by embedding fan-outs in logic gates, making them partially reversible. Simulation results for state-of-the-art benchmarks indicate an average reduction of the fundamental energy limit by 44% without affecting the delay. If delay is not the main concern, the average reduction reaches even 77%. To the best of our knowledge, this paper presents the first post-synthesis strategy to reduce fundamental energy limits for field-coupled nanocomputing circuits by means of logic network changes.
local.publisher.countryBrasil
local.publisher.departmentENG - DEPARTAMENTO DE ENGENHARIA ELETRÔNICA
local.publisher.departmentICX - DEPARTAMENTO DE CIÊNCIA DA COMPUTAÇÃO
local.publisher.initialsUFMG
local.url.externahttps://ieeexplore.ieee.org/document/8723304

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