Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement
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Universidade Federal de Minas Gerais
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As systems grow in complexity and extension, the analysis and comprehension of their dynamics becomes proportionally harder, reducing their reliability [1]. Currently, the most common and effective way to deal with faults is through redundancy, although it presents no self-adaptability and is subject to the availability of resources. In this context, it is proposed the investigation and implementation of bio-inspired hardware solutions. It is possible to find systems optimal configurations through the concept of evolution. Therefore, the purpose of this research is to reproduce a novel architecture [2] and analyze the Evolvable Hardware behavior in a FPGA with the capability to self-heal through the search and selection of new optimal hardware configurations assisted by a Genetic Algorithm in order to recover from a hardware service failure caused by component faults [3]. Thereby, it was implemented as a proof of concept a BCD decoder design, which presented a 100% output accuracy and was able to self-adapt, repairing failures caused by simulated faults in up to 35.9% of the cells. The recovery time is affected by the hardware architecture and the evolution operators. Finally, this research concludes that evolvable hardware is a promising alternative for autonomous design and fail-safe digital systems, although it still has potential for improvement and has limited scalability.
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Hardware (Computadores), Circuitos integrados digitais - Projetos e construção
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Hardware , Circuit faults , Genetic algorithms , Reliability , Table lookup , Complexity theory, Fault Tolerance , Bio-Inspired , Evolvable Hardware , Genetic Algorithm , Adaptative Systems, Evolvable Hardware , Recovery Time , Algorithm In Order , Hardware Architecture , Evolution Operator , Evolutionary Concepts , Defects In Components , Fault Simulation , Search Algorithm , Evolutionary Algorithms , Functional Unit , System Output , Fault-tolerant , Lookup Table , Digital Circuits , Elimination Technique
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https://ieeexplore.ieee.org/document/8349669